1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor integrated circuit device employing the semiconductor memory device. In particular, the invention relates to a semiconductor memory device capable of implementing efficient redundancy-based repair when any defect occurs in a memory cell, and to a semiconductor integrated circuit device employing such a semiconductor memory device.
2. Description of the Background Art
As a semiconductor memory device capable of processing a large amount of data at a high speed, a memory chip is now being developed having a logic circuit and a DRAM (Dynamic Random Access Memory) both mounted on one chip (hereinafter referred to as "embedded DRAM"). While data is conventionally transferred between a logic circuit represented by a processor (MPU) and a memory portion represented by the DRAM via an I/O pin and a data bus, the embedded DRAM aims to enhance data transfer rate (access speed and memory band width) between its processor and DRAM by transferring data via a memory bus mounted on the memory chip.
Concerning a semiconductor memory device having a large scale memory cell array, a redundancy-based repair scheme is important in order to enhance yield in manufacture. By the redundancy-based repair (hereinafter referred to simply as redundancy repair), a defective portion of a memory cell generated in manufacture is repaired using a spare memory cell in a redundant circuit that is preliminary mounted on the same chip.
Although the data transfer rate between the logic portion and the memory portion can be improved in the embedded DRAM, the logic circuit and the memory circuit mounted on the same chip considerably limit the layout, and thus it is an object of the embedded DRAMI to enhance the degree of integration relative to both of the circuits.
A fuse element is used for programming a defective address in the redundancy repair scheme. The fuse element occupies a relatively large area which is inappropriate for enhancement of integration, and thus significantly influences the layout design. If the same redundant circuit is shared by a plurality of banks for reducing the number of fuse elements, a large number of switching circuits are required for transferring data between data I/O lines and the redundant circuit in input and output of data, leading to limitation of layout.
In order to achieve an object of reducing the layout area, which is one of the important objects for the embedded DRAM, it is highly important to efficiently arrange a redundant circuit.
For execution of the redundancy repair, a redundancy judgement is first made by comparing an input address signal with a defective address stored in a fuse element and determining if they match with each other. An actual access operation is then carried out by determining an address to which an access is to be made. Accordingly, an additional cycle is required for the redundancy judgement each time the access operation is done. In the embedded DRAM aiming to achieve enhanced-speed data processing, it is important to make the redundancy judgement more efficiently in relation to the timing to reduce the time necessary for the judgement and thus improve the operating speed.